This invention generally relates to data processing systems and, more specifically, to a central processor that is adapted from processing addresses in one address section (local addressing) to processing addresses in several address sections (extended or global addressing).
A conventional central processor for a data processing system has a fixed address space that determines the maximum virtual memory which can be addressed by the virtual processor. For example, in the DECsystem-10, manufactured by Digital Equipment Corporation, the address space is 18 bits and the virtual memory, which is directly addressable without index modification, would be 256K of memory locations.
The previously referenced PDP10 Reference Handbook specifically describes a process for generating "effective" addresses of virtual memory locations in the DECsystem-10. In this system, an instruction contains an instruction code field, an accumulator address field, an address type (I) field, an index register address (X) field and a memory address (Y) field. The Y field contains eighteen bits. An index register contains thirty-six bits; however, only eighteen bits are used as an index value. The other eighteen bits can be used for some other purpose, such as counting. Whenever an instruction is processed, the contents of the I, X and Y fields, or addressing fields, must be used to produce an effective address that identifies the location of the operand in the system. If the X field is not zero, the index value from an index register identified by the X field is added to the contents of the Y field to obtain a modified address. If the X field is zero, no indexing occurs, and the modified address and the contents of the Y field are identical. If the I field is zero, the addressing is "direct" and the modified address is the effective address of the desired virtual memory location.
If the I field is not zero, the addressing is indirect, so the system retrieves a new word from the location identified by the modified address. This new word also contains I, X and Y fields in locations that correspond to the locations of the instruction word in the system. They are processed in the same manner as the fields in the instruction are processed. That is, the X and Y fields determine the effective address if the I field is zero; otherwise the X and Y fields determine the address of another new word. New words continue to be obtained for calculating effective addresses until a word is obtained with an I field value of zero. Then the eighteen-bit number calculated from that word is the effective address of the desired virtual memory location.
In this system, any carry from the addition of the index value and the contents of the Y field is disregarded, so all effective addresses are limited to eighteen bits. This defines the same address space that can be defined by the Y field, and locations within the defined 256K locations are said to be in the local virtual address space.
Normally, if a program is larger than the local virtual address space, memory address management for the program's memory address space is required. In prior systems, a memory management system is provided that allows overlays of the various program routines into virtual memory. Each such overlay divides the information into pages which can then be read from virtual memory. The central processor then, via tables in a mapping scheme, determines the actual, or physical, location which should be referenced. Obviously, as more routines are used by the central processor, the physical memory becomes completely used and swapping of the routines into the physical memory is required. However, by overlaying and using swapping, the central processor "believes" that it has a much larger virtual memory than actually existed. The problem is compounded when one realizes that the data referenced by the routines may also be included in the memory space. The problem with overlaying is that one must figure out how to break up the routines into appropriate overlays. With the instant invention, a larger virtual address space is provided thereby alleviating the problems of overlaying and swapping.
Another prior art system uses a base register to increase the size of the virtual memory. However, this prior art system is static in that once the size of the virtual memory has been established by the base register, all memory references are made based upon the address size identified in the base register. While this somewhat alleviates the problem of an increased virtual address space, it also increases the complexity for any effective address calculation. Obviously, it would be desirable to have a system which can switch from one state to another depending upon the needs required at the moment.